Technical Field
Embodiments of the present disclosure generally relate to the field of display technologies, and particularly, to an array substrate and a method of manufacturing the same, and a display panel.
Description of the Related Art
TFT-LCDs become dominant in current market of flat panel display due to their advantages such as small volume, light weight, low power consumption, no radiation and the like. A TFT-LCD display screen generally includes an array substrate, a color filter base substrate and liquid crystal therebetween. The TFT-LCD display screen is provided with hundreds of thousands to millions of display units arranged in an array, and each display unit displays an image under control of TFT. It is desired to further improve yield of the display unit.
Exemplarily, as shown in FIG. 1, there is shown a schematic diagram of a display unit on an array substrate of an existing TFT-LCD display screen, and a plurality of gate lines 121 and data lines 16 are formed on the array substrate, the gate lines 121 and the data lines 16 cross each other to define a display unit. FIG. 2 is a schematic diagram taken along line a-a′ shown in FIG. 1. As shown in FIG. 2, the array substrate comprises: a base substrate 11; a gate electrode (a portion of the gate line 121) and a common electrode line 122 formed on base substrate 11; a gate insulating layer 13 covering the gate electrode 121 and the common electrode line 122; an active layer 14, a source electrode 161 and a drain electrode 162 formed on gate insulating layer 13; a passivation layer 15 and a pixel electrode 17 formed on the passivation layer 15; a planarization layer 18 and a common electrode 19 formed on the planarization layer 18. Generally, the common electrode 19 is connected with the common electrode line 122 through a through hole 1 through the planarization layer 18, the passivation layer 15 and the gate insulating layer 13, and the pixel electrode 17 is connected with drain electrode 162 through a through hole 2 in the passivation layer 15.
It has been found by inventors that for the existing array substrate, as shown in FIG. 2, since the through hole 1 penetrates through the planarization layer 18, the passivation layer 15 and the gate insulating layer 13, the through hole 1 has a larger depth, so that a connection between the common electrode 19 and the common electrode line 122 will easily be broken, resulting in a poor display effect and reduction in yield of product.